U.S. Pat. No. 5,524,092 describes a multilayered ferroelectric-semiconductor memory device, in which two different values of the capacitance of the device are available, depending on the direction of the polarization of the ferroelectric layer. To this end, a ferroelectric-semiconductor interface is provided. Determining the capacitance of the structure allows to derive the polarization state of the ferroelectric layer without changing it. This way, information can be stored and nondestructively read. However, the layer structure of U.S. Pat. No. 5,524,092 is rather complicated. Furthermore, it has been proven technologically difficult to fabricate layer structures with a semiconductor material such as silicon adjacent to a ferroelectric. This reduces the choice of materials and requires the use of materials, which are not typically integrated into an industrial fabrication process. This in turn increases the processing cost.
U.S. Pat. No. 5,262,983 discloses a memory comprising a ferroelectric capacitor. Application of an external voltage generates respective space charge regions proximate to a respective interface between the ferroelectric and each electrode. Sandwiched between the space charge regions, an uncharged region of the ferroelectric remains. The ratio of the extensions of the uncharged regions of the ferroelectric material and of the space charge regions in the direction of the layer sequence influences the capacitance. A hysteresis of the capacitance vs. voltage is effected by a superposition of the internal polarization of the ferroelectric and of the polarization of the space charge regions under application of an external electric field. A number of distinguishable, stable states for storing values can be provided this way.
A write signal has a bias voltage greater than the coercive voltage of the ferroelectric layer. Two situations can be distinguished:    a) The bias voltage establishes an electric field that is additive with the internal polarization field. This increases the size of the space charge region, with a concomitant decrease in capacitance.    b) The bias voltage establishes an electric field that is subtractive to the internal polarization field. This decreases the size of the space charge region, with a concomitant increase in capacitance.
The actual capacitance value assumed by the capacitor depends on the history of the bias voltage. A larger capacitance is achieved after scanning the bias voltage to a negative voltage larger than the coercive field. A smaller capacitance is achieved by scanning the bias voltage to a positive value larger than the coercive field of opposite polarity.
There are several issues that render the device described in U.S. Pat. No. 5,262,983 undesirable for application in the field.
First, if the space charges are immobile at high frequency, then the full layer stack will always have the same capacitance. Accordingly, the space charge regions have to be electrically conductive at the desired frequency of operation. They in effect behave as semiconductor regions. It is known that ferroelectric materials can be made semiconductive. Semiconductor materials allow the formation of a depletion layer, which can act as a capacitance sensor. In other words, in the device of U.S. Pat. No. 5,262,983, the capacitance is not defined by the neutral zone in the ferroelectric layer, but by the extension of the depletion layer in the space-charge region. As a result, the layer structure of this document resembles that of U.S. Pat. No. 5,524,092 and shares its disadvantage of high complexity.
Second, in the device of U.S. Pat. No. 5,262,983, a non-zero bias voltage has to be applied in a read operation to differentiate between capacitance states.
It would be desirable to provide a capacitive structure for an electric component that does not require the application of a bias voltage for determining the capacitance state.